Evaluating the hardware cost of posit arithmetic

Évaluation du coût de l'implantation matérielle de l'arithmétique posit

Luc Forget (1) , Yohann Uguen (1) , Florent de Dinechin (1)

1 CITI - CITI Centre of Innovation in Telecommunications and Integration of services

The posit number system is an elegant encoding of floating-point values, recently proposed as a drop-in replacement for the IEEE-754 floating-point standard. It is more regular and simpler than IEEE-754, discarding many of its less used features, such as subnormals, Not-a-Numbers, signed infinities, or directed rounding modes. Posit arithmetic consistently rounds to nearest even, with overflows managed by saturation. It also offers tapered precision, where numbers near 1 have more significand bits than very large or very small ones (and more significand bits than IEEE-754 for the same word size). For applications whose data is consistently within this accurate region, posits offer more accuracy for the same word size, while accuracy may be degraded for other applications. A common claim of the posit literature is that posits, being simpler than IEEE-754, are also cheaper to implement. This article refutes this claim. In the same context, posit operators are shown to be intrinsically both larger and slower than IEEE-754 operators of the same size. A first reason is that posits must be decoded into some kind of floating-point before being processed, then they must be reencoded. This article develops a solution where posits are kept decoded in processor registers to avoid paying the decoding/encoding overhead for each operation, using an original in-register rounding approach to avoid double rounding issues. A second reason is that the extra accuracy of posits requires a wider data-path. For instance, the processor registers must be wider than posits themselves if the previous solution is used. Compared to these two overheads, the overhead of managing directed rounding modes, infinities or NaNs in IEEE-754 operators is very small. Unbiased quantitative comparisons support this analytical study. For this purpose, this work introduces an open-source library of basic parametrized operators (for addition/subtraction, multiplication, and exact accumulation) for posit and IEEE-754. All the operators are developed with the same high design effort, using the same tools and libraries, and are fully compliant to their respective standards. This library is first shown to improve the state of the art of posit operators. Despite this, a comparison on FPGAs shows that posits arithmetic has an overhead between 30% and 60% both in area and delay compared to IEEE-754 for the same data size.

Domaines: Architectures Matérielles [cs.AR]; Arithmétique des ordinateurs

Luc Forget, Yohann Uguen, Florent de Dinechin. Evaluating the hardware cost of posit arithmetic. 2021. ⟨hal-03195756v1⟩